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The 65xx family of computer processors have 8- and 16-bit architectures, use low power, and are used in high volumes, mostly in embedded systems. The line began with the 6501, and 6502, which were designed mostly by the same engineering team that did the Motorola 6800. They quit Motorola unitedly, and quickly designed new devices that competed with the Motorola 6800, and Intel 8008 and 8080, but cost far less. The 6502 powered many early video games, and personal computers, PCs: Apple I, II (not IIgs), III; Atari 400, 800; Commodore PET, 64, 128D; Acorn Microcomputer; Franklin ACE 1200.
The term 68k means the Motorola 68000 series processors. Some variants: 68000, 68010, 68020, 68030, 68040, 68060; CPU32 (68330), 68360 (QUICC), ColdFire, DragonBall. These were and are used in many: Personal computers: Apple Macintosh, Commodore Amiga, Atari ST, early HP 9000s; Workstations: Sun Microsystems Unix, Apollo/Domain. Video games: Sega Genesis/MegaDrive, NeoGeo, several arcade machines. Many versions are in production, as embedded processors.
Alpha is a RISC CPU that was created by DEC: Digital Equipment Corp. When DEC merged with Compaq, the Alpha went with them, so now Compaq sells Alpha. Alphas are among the fastest microprocessors generally available.
ARM is an acronym for Advanced RISC Machines. These processors are named after the firm that first made them: Advanced RISC Machines Ltd. Then ARM (Ltd.) sold a license for the ARM (architecture) to DEC (Digital Equipment Corp.), which named their variant StrongARM. Then DEC sold their division that made StrongARM to Intel, who now makes StrongARM. Now you can get ARMs from ARM and Intel, but not DEC. Simple, yes?
Synchronous processors have one central clock, which synchronizes and coordinates the progress of operations throughout a processor. Synonym: clocked. All parts and stages work to its unifying beat signal, at the same rate, in lock step, handing off work to the next stage as the clock ticks. Almost all computers made, and in use, are synchronous. Clock speed is a primary performance trait. For personal computers, it is used as an identifier and for marketing, shown in units of megahertz (MHz) or gigahertz (GHz). Asynchronous processors have no clock. Synonyms: asynchronous logic, clockless, unclocked; self-timed; hand-shaking. All parts and stages work independently, handing off work to the next stage as it is finished. Different stages stop between tasks. All stages can work at the same or different rates. This is more complex to implement, but lowers power use, current peaks, and emitted heat and electromagnetism (raising security). Only a small fraction of computers made, and fewer in use, mainly in embedded systems, are asynchronous.
The AVR RISC microcontroller family is made by Atmel Corp. It uses a RISC core running single cycle instructions, and a well defined I/O structure that limits need for external components. Some features in AVR devices: internal oscillators, timers, UART, SPI, pull-up resistors, pulse width modulation, ADC, analog comparator, watch-dog timers. The architecture was created at the Norwegian Institute of Technology (NTH), by two students: Alf-Egil Bogen, Vegard Wollan, and developed further at Atmel Norway AS, a subsidiary founded by them. The chip is supported by Atmel, and by a vibrant, large, and growing user community, which provides free projects, software, tutorials, and much other assistance.
Barrel processors switch between execution threads on every machine cycle. This is also known as interleaved or fine-grained multithreading. Like preemptive multitasking, each executing thread is assigned its own program counter and other registers (each thread's architectural state). But, barrel processors guarantee that each thread can execute one instruction every N cycles. In contrast, preemptive multitasking usually runs one thread for hundreds or thousands of cycles while all other threads wait a turn.
Bit slice processors are modules used to build up larger processors. A larger processor of word size X is built up of several smaller modules, ALUs (Arithmetic and Logic Units), of word size usually X/16, X/8, X/4, or X/2; i.e., of 1, 2, 4 or 8 bits. Due to microlithography advances, this is now mostly obsolete technically, and of historical interest. Most bit slicing occurred from the mid-1970s to the mid-1980s, when integrated circuit chips were too small to hold all of the circuitry needed for a full larger processor (usually 16- to 32-bits), during the time of medium scale integration (MSI), and early large scale integration (LSI).
Cellular Automata (CA) processors are a physical, not software only, implementation of CA concepts, which can process information computationally. Processing elements are arranged in a regular grid of identical cells. The grid is usually a square tiling, or tessellation, of two or three dimensions; other tilings are possible, but not yet used. Each cell is in one of a finite number of states, determined only by interactions with the small number of adjoining cells. Cells interact, communicate, directly only with adjoining, adjacent, neighbor cells. No means exists to communicate directly with cells farther away. Cell interaction can be via electric charge, magnetism, vibration (phonons at quantum scales), or any other physically useful means. This can be done in several ways so no wires are needed between any elements. This is very unlike processors used in most computers today, von Neumann designs, which are divided into sections with elements that can communicate with distant elements, over wires.
CISC is an acronym for Complex Instruction Set Computer. It is a processor design philosophy favoring larger and more complex sets of instructions, that usually execute in many, and varying numbers of, clock cycles and varying amounts of time. This makes programs slower, and smaller, needing less bus bandwidth, memory (RAM), and storage (disk). Common CISC processors (and original makers): 68k (Motorola), TRON, x86 (Intel), Z-80 (Zilog).
The DLX is a reduced instruction set computer (RISC) processor architecture. It is mainly a cleaner, simpler MIPS architecture, with a simple 32-bit load/store design, and intended mainly for education, as are Donald Knuth's MIX and MMIX architectures. All three are widely used in college-level computer architecture courses. DLX was introduced in the textbook "Computer Architecture: A Quantitative Approach", by John L. Hennessy and David A. Patterson, the main designers of the MIPS and Berkeley RISC designs, respectively, which are the two benchmark RISC designs.
To this category, please submit only links on processors, central processing units (CPUs), which were created, and have as a main or major purpose, to educate and teach about computer concepts, design, programming, and/or larger, more general system issues; and/or support other types of education (networking, mathematics, physics); processors existing solely or in large part, to educate. Submit links about education for specific processors to a category for such. Examples: RISC processor education must go to a RISC category. MIPS processor education must go to a MIPS category.
This category covers processors, central processing units (CPUs), which were created, and have as a main or major purpose, to educate and teach about computer concepts, design, programming, and/or larger, more general system issues; and/or support other types of education (networking, mathematics, physics); processors existing solely or in large part, to educate. Mostly the links in this category point to other processor categories and processors there. The only processors listed exclusively here are those for which no better or clearer category seems suitable.
The iAPX-432 was Intel's first 32-bit processor, released in 1981 as a set of 3 integrated circuits. It was to be their main architecture of the 1980s. It was very innovative, and complex, with direct hardware and microcode support for advanced multitasking, memory management, data structures, security, object-oriented and capability-based programming, and multiprocessing with up to 64 processors. Modern operating systems could be implemented in far less program code than for normal processors, because it did so much work internally in hardware. Intel called it the Micromainframe.
This category is for minimal processors: CPUs that use various design strategies to strongly minimize the component count needed to do work; to be as simple as possible. This includes: MISC (Minimal Instruction Set Computers), SISC (Simple Instruction Set Computers), ROSC (Removed Operand Set Computer), ZISC (Zero Instruction Set Computers), Forth and stack processors, and other methods. This was one of the original goals of RISC (Reduced Instruction Set Computers), but many newer RISC processors are more complex than the original CISC (Complex Instruction Set Computers) processors they challenged, and some current CISC processors are astonishingly complex. Minimal processors will be very useful in, and may become important for, mobile and ubiquitous computing.
MIPS is an acronym for: Microprocessor without Interlocked Pipeline Stages. It is a RISC processor architecture, developed by MIPS Computer Systems, Inc. Uses: Cisco routers, video games (Nintendo 64; Sony PlayStation 1, 2, Portable handhelds), Windows CE devices, SGI computers, many embedded systems. By the late 1990s, about 1 in 3 RISC chips were MIPS-based.
Multiprocessors are processors made of two or more processing subunits; single computers containing more than one processor. There is no one model or configuration for these. The term's meaning varies with context, mainly by how processors are defined or implemented: many cores on one chip (multicore), many chips in one chip carrier (package), many carriers on one board, many boards in one system unit, many system units in one room, many rooms in one building, etc. Key trait: all subprocessors are treated, and work, together in some manner, as one processing unit, during some task. This is well suited to problems that can be processed as Multiple Instruction, Multiple Data: MIMD. Some single personal computers now have two or four processors. Giant single supercomputers can have 64,000 (Connection Machine) processors, or more.
Nios is a soft configurable RISC processor, designed for field programmable gate arrays (FPGAs), for embedded uses, by Altera Corp. The 16-bit, first version is called Nios, the 32-bit version is called Nios II. Altera suggests the later for all new design work. By being soft-core, FPGA developers can choose from many system configurations, using the best-fit core, and peripherals.
This category holds links on computer central processors for which one or more: body of writing, specification, or implementation exists, that meet the definition of open source software found at Opensource.org; they are developed and licensed openly and freely.
The PA-RISC (Precision Architecture Reduced Instruction Set Computing), a.k.a. HP/PA (Hewlett Packard Precision Architecture) was developed by Hewlett-Packard's Systems & VLSI Technology Operation in the late 1980s. Most versions have no Level 2 cache. Instead, large Level 1 caches are used, first as separate chips connected via bus, and now integrated on-chip.
Parallel processors are computers that can do more than one operation at once, concurrently, during the same cycle. Some have more than one processor; others have one processor that handles large amounts of data with each cycle. Parallel computers can run some types of programs far faster than traditional single processor computers, often termed the von Neumann architecture.
PIC is a family of RISC microcontrollers made by Microchip Technology, derived from the PIC1650, originally developed by General Instrument's Microelectronics Division. PICs use a Reduced instruction set, varying in length from about 35 instructions at the low-end, to about 70 instructions at the high-end. The set includes instructions to perform many operations on the accumulator. and a constant or the accumulator and a memory location, and for conditionally executing code and jumping/calling other parts of the program and returning from them, and specific hardware features like interrupts, and a low power mode called sleep. Microchip provides a freeware IDE package called MPLAB, with a software simulator and assembler.
To this category, please submit links only on IBM''s POWER processor, PowerPC, Cell, and closely related topics.
POWER is an acronym for: Performance Optimization With Enhanced RISC; a RISC (Reduced Instruction Set Computer) architecture central processor, designed, produced, and sold by International Business Machines: IBM. It is the basis for, and remains similar to, two better known processors and brands: 1) The PowerPC processor, used in: later Apple Macintosh personal computers, some IBM workstations, later Microsoft game computers (Xbox 360); and many embedded applications. 2) The Cell processor, a 9 core multiprocessor, on one chip.
Reconfigurable processors process information via normal (von Neumann) processors used with highly flexible computing fabrics often made of field-programmable gate arrays, FPGAs. Normal processors can reconfigure (make changes to) software (programs, control flow), but not hardware (data paths). Reconfigurable processors can reconfigure control flow, and data paths. Reconfiguration can occur during deployment, between execution phases, or during execution. In typical reconfigurable systems, a bit stream is used to program devices during deployment. These often achieve a 10-100 fold increase in computing density and speed (reduced latency) over normal processors.
Reversible or adiabatic computing/logic uses processors that can reconstruct a prior state of a computation, from a later state; they are time-invertible, can produce time-reversed version of a process; run it backwards. The main reason to do this to save energy, and lower heat output, by using thermodynamically reversible, energy-recovering circuits and devices. This is a research area which is gaining interest (heating up), as processors grow smaller and faster, and thus hotter per unit area.
RISC is an acronym for Reduced Instruction Set Computer. It is a processor design philosophy favoring smaller and simpler sets of instructions, that all execute in one, and the same number of, clock cycles and same amount of time. This makes programs faster, and larger, needing more bus bandwidth, memory (RAM), and storage (disk). Common RISC processors: ARM, DEC Alpha, IBM POWER, PA-RISC, MIPS, SPARC. RISC research began with a discovery. In traditional CPU designs, CISC (Complex Instruction Set Computer), many programs running on them were ignoring many instructions that existed to facilitate coding. The more complex instructions took several processor cycles to execute. CPUs were growing faster relative to the memory they accessed. This led to many methods to streamline processing in CPUs, while trying to lower the number of memory accesses.
SPARC is an acronym for Scalable Processor ARChitecture. It is a RISC (Reduced Instruction Set Computing) design created and licensed by Sun Microsystems, Inc. RISC work began at Sun in 1984, by Bill Joy and Dave Patterson, and the first SPARC was introduced in 1987. It is widely licensed and used.
The SuperH (SH) is a microprocessor/controller architecture. It is basically a 32-bit load/store RISC core design, with a 16-bit instruction set, but 32-bit register length and data paths. This gives high code density; in the 1990s, memory was very expensive. It was first developed by Hitachi in the early 1990s. They were developing a full set of instruction set upward compatible cores. The first, SH-1 and SH-2 were used in the Sega Saturn and 32X game consoles, and then later in many other microcontrollers used in many other embedded systems. Many processors and controllers are based on this core family. It is used in many embedded systems.
Transmeta: a highly secretive California firm working on a microprocessor that will emulate many microprocessors, though its main target seems to be Intel's Pentium. It is claimed the Transmeta chip is faster than a Pentium Pro, but with only 1/4 the components. Ironically, the secretive Transmeta employs Linus Torvalds, creator of the open and free Linux OS.
Transputer is a word meaning transistor computer. It is officially spelled with lower case. It was made by British semiconductor firm INMOS Ltd. It was the first general purpose microprocessor intended to be used in parallel multiprocessor computers. It was to be a range of chips of varying power and cost, that were assembled to form a full computer. The name indicated the role that individual transputers had: they would be used as basic building blocks, as transistors had been.
A TRON processor is any processor with a core based on the free specifications defined by the Japanese TRON Project, an acronym for: The Real-time Operating system Nucleus. The processors are to be the main hardware building block of the TRON Hypernetwork (Highly Functional Distributed System: HFDS), the final goal of the TRON Project. These CPUs use a VLSI (very large scale integration), 32-bit CISC (complex instruction set computer) architecture. Using CISC minimizes the object code size of programs to minimize RAM (random access memory) needs and cost. Several versions exist, made by different firms, mainly for embedded systems, often as cores for devices based on ASIC/ASSP (application-specific integrated circuit, application-specific standard product).
VLIW is an acronym for: Very Long Instruction Word. This processor architecture implements a type of instruction level parallelism; multiple words executed per processor cycle. Similar to superscalar methods and architectures, it uses several execution units (e.g. 2 multipliers), so processors can execute several instructions at once (e.g. 2 multiplications). It is well suited to problems that can be processed as Single Instruction, Multiple Data: SIMD.
Wherever possible, please submit links on CPUs to extant Open Directory categories on those CPUs. Thank you.
This category holds links on Intel and compatible x86-based architecture central processor units: CPUs. Main members of the Intel x86 family: 8086, 8088, 80186, 80286, 80386, 80486, 80586 (Pentium), 80686 (Pentium II), 80786 (Pentium III), 80886 (Pentium 4), and more to come. Some x86 compatibles: AMD, Cyrix, Transmeta, Winchip, etc.
The Z80 family of processors began as an 8-bit microprocessor, a compatible, improvment on the Intel 8080. It was originally created by ZiLOG, Inc., and began selling in July 1976, two years before the Intel 8088. The Z80 was used and copied widely, and dominated the 8-bit market from the late 1970s to the mid-1980s. Many early desktop PCs were based on it: Amstrad CPC, PCW series; Enterprise 128; Jupiter Ace; MSX; Radio Shack TRS-80; Sinclair ZX80, ZX81, ZX Spectrum; Tatung Einstein. The Z80 was not used by Apple (used MOS Technology 6502), or IBM (used Intel 8088). It saw even wider use in embedded computers, including defense systems, and is still common in these today.
ZISC is an acronym for Zero Instruction Set Computer. It is a processing method based on: pattern matching only, with no (micro-)instructions of any usual type, using ideas from artificial neural networks. The acronym derives from the previously named RISC: Reduced Instruction Set Computer. It was jointly developed by Dr. Pascal Tannhof of IBM of Paris, and Silicon Recognition, Inc., of California.
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Last update: Friday, May 4, 2012 9:05:05 AM EDT - edit