High Level Synthesis (or Behavioural Synthesis) is automatic compilation (translation) from a description which is relatively easy to write and read to a representation that can be automatically implemented. The most common synthesis today compiles from a register transfer level language (RTL) to a netlist of existing design fragments (cells, gates, CLBs) in an ASIC/FPGA technology. High Level Synthesis is distinguished from RTL Synthesis by starting from a more abstract description, which takes less effort to write and is easier to read and understand. Thus the High Level Synthesis tool takes over more of the design work.
Last update:January 2, 2007 at 18:00:25 UTC