RISC is an acronym for Reduced Instruction Set Computer. It is a processor design philosophy favoring smaller and simpler sets of instructions, that all execute in one, and the same number of, clock cycles and same amount of time. This makes programs faster, and larger, needing more bus bandwidth, memory (RAM), and storage (disk). Common RISC processors: ARM, DEC Alpha, IBM POWER, PA-RISC, MIPS, SPARC. RISC research began with a discovery. In traditional CPU designs, CISC (Complex Instruction Set Computer), many programs running on them were ignoring many instructions that existed to facilitate coding. The more complex instructions took several processor cycles to execute. CPUs were growing faster relative to the memory they accessed. This led to many methods to streamline processing in CPUs, while trying to lower the number of memory accesses.
Related categories 3
John Mashey on RISC/CISC
From comp.arch debates, in one text document for easier reading, original text and formats preserved, mostly.
Reduced Instruction Set Computer
Brief, very clear definition, with links to related issues and processors. FOLDOC.
What is RISC?
Defines term, lists other webpages. Webopedia.
Wikipedia: Reduced Instruction Set Computer
Online encyclopedia article about RISC.
Beyond RISC: The Post-RISC Architecture
Today's RISC processors are so far from RISC roots that they are no longer truly RISC. Michigan State University, Department of Computer Science. (May 01, 1996)
Other languages 1
Last update:June 4, 2012 at 5:54:05 UTC