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Computers: Hardware: Components: Processors: MIPS
Computers: Hardware: Components: Processors: RISC
Computers: Programming: Education
Computers: Programming: Languages: Assembly: MIX-MMIX
Computers: Programming: Languages: Education
Computers: Software: Operating Systems: Education
Science: Technology: Electronics: Design: Hardware Description Languages: VHDL
The DLX Instruction Set Architecture Handbook
- By Philip M. Sailer, David R. Kaeli; Morgan Kaufmann, 1996, ISBN 1558603719, 1st edition. Definitive work on DLX instructions. Information and abstract. ACM Portal.
- ASynchronous, open source, Processor IP of the DLX Architecture. Goal: show feasibility to design and deliver asynchronous open IPs in portable, re-usable way. Information, downloads. Open source hardware.
David R. Kaeli, Professor
- Director of Northeastern University Computer Architecture Research Laboratory, and co-author of Computer Architecture: A Quantitative Approach. Professional information with some links.
DLX in VHDL
- VHDL model of processor; most instructions use 5 clock cycles to run, jumps use 3, floating point timing not fully accurate because fp instructions also take 5 cycles to run; description, download.
- Documents: getting started, instruction set summary and description, simulator manual.
DLX Instruction Slides
- Tables of instructions, categorized, as PDF slides. By Guy Even, Tel Aviv University. [PDF]
The DLX Processor
- Class overview with tables (instruction format, set) and diagrams (timing), some other information. By Ethan Miller, University of Maryland.
Implementation of 5-stage DLX Pipeline
- Introductory tutorial with definitions, explanations, examples to show basic pipelining ideas; applet simulation lets users choose instructions to run, and see how pipeline works from direct experience.
Introduction to Operating Systems
- DLXOS information needed for programming, from introductory course on OSs.
Norman Matloff's DLX Tutorial
- Information on DLX processor simulator and compiler, DLXsim, interactive program, loads assembly programs and simulates operation of computer on them, single-stepping or continuous execution.
Out of Order Execution
- Master's Thesis: Design and Evaluation of a RISC Processor with a Tomasulo Scheduler. Uses DLX. HTML, PS, GZ, PDF.
Superscalar DLX Processor
- Diagram, description, download.
- Encyclopedia article with links to many related topics.
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